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2019WP/HPC-10_Mike_Tiling – NEMO
wiki:2019WP/HPC-10_Mike_Tiling

HPC_10_Mike_tiling

Last edition: Wikinfo(changed_ts)? by Wikinfo(changed_by)?

The PI is responsible to closely follow the progress of the action, and especially to contact NEMO project manager if the delay on preview (or review) are longer than the 2 weeks expected.

  1. Summary
  2. Preview
  3. Tests
  4. Review

Summary

Tiling as a solution to cache blocking: implementation proposal

https://forge.ipsl.jussieu.fr/nemo/ticket/2198#ticket

  • Build demonstration branch for the ST
  • investigate solution for routine with lbclnk in it (advection for example)
  • Test SETTE configuration to highlight possible issue with AGRIF, BDY, iceberg, OASIS …

This work

  • depends on implementation of an extended halo
  • depends on and will influence the implementation of the DO loop macros
  • depends on development of XIOS to accept 2D tiles of data
  • will be done by Daley Calvert in collaboration with Andrew Coward, Italo Epicoco, Gurvan Madec and Francesca Mele.

Preview

Error: Failed to load processor box
No macro or processor named 'box' found

Tests

Error: Failed to load processor box
No macro or processor named 'box' found

Review

Error: Failed to load processor box
No macro or processor named 'box' found
Last modified 2 years ago Last modified on 2019-12-18T11:48:42+01:00